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SN74LV2T74PWR

Name: Texas Instruments SN74LV2T74PWR
Brand: Texas Instruments
SKU: 595-SN74LV2T74PWR
Price: 39.15 INR
Availability: InStock

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Mouser No:

595-SN74LV2T74PWR

Mfr. No:

SN74LV2T74PWR

Mfr.:

Texas Instruments

Description:

Flip-Flops 1.8-V to 5.5-V singl e power supply dual

Datasheet:

SN74LV2T74PWR Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments SN74LV2T74PWR

In Stock: 2,905

Stock:: 2,905 Can Dispatch Immediately

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Factory Lead Time:: 6 Weeks Estimated factory production time for quantities greater than shown.

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Minimum: 1 Multiples: 1

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Ext. Price:

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Packaging:

Full Reel (Order in multiples of 3000)

Cut Tape

MouseReel™ (+₹475.00)

Pricing (INR)

Qty.	Unit Price	Ext. Price
Cut Tape / MouseReel™ ^†
	₹39.15	₹39.15
	₹27.14	₹271.40
	₹24.27	₹606.75
	₹21.05	₹2,105.00
	₹19.49	₹4,872.50
	₹18.62	₹9,310.00
	₹17.84	₹17,840.00
Full Reel (Order in multiples of 3000)
	₹16.79	₹50,370.00
	₹16.36	₹98,160.00

† A MouseReel™ fee of ₹475.00 will be added and calculated in your basket. All MouseReel™ orders are non-cancellable and non-returnable. ↩

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Flip-Flops
RoHS:
Logic Family:	LV
Package/Case:	TSSOP-14
Input Type:	CMOS
Supply Voltage - Min:	1.6 V
Supply Voltage - Max:	5.5 V
Mounting Style:	SMD/SMT
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Reel
Packaging:	Cut Tape
Packaging:	MouseReel
Brand:	Texas Instruments
Country of Assembly:	Not Available
Country of Diffusion:	Not Available
Country of Origin:	CN
Number of Input Lines:	2 Input
Number of Output Lines:	2 Output
Product Type:	Flip Flops
Series:	SN74LV2T74
Factory Pack Quantity:	3000
Subcategory:	Logic ICs

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Datasheet

SN74LV2T74PWR Datasheet

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CAHTS:: 8542390000
USHTS:: 8542390090
TARIC:: 8542319000
MXHTS:: 8542399999
ECCN:: EAR99

SN74LV2T74/SN74LV2T74-Q1 Dual D-Type Flip-Flop

Texas Instruments SN74LV2T74/SN74LV2T74-Q1 Dual D-Type Flip-Flops contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q, Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q, Q). The output level is referenced to the supply voltage (V_CC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.