EPM240GT100I5N

Altera
989-EPM240GT100I5N
EPM240GT100I5N

Mfr.:

Description:
CPLD - Complex Programmable Logic Devices

ECAD Model:
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In Stock: 265

Stock:
265 Can Dispatch Immediately
Factory Lead Time:
2 Weeks Estimated factory production time for quantities greater than shown.
Minimum: 1   Multiples: 1
Unit Price:
₹-.--
Ext. Price:
₹-.--
Est. Tariff:

Pricing (INR)

Qty. Unit Price
Ext. Price
₹1,947.93 ₹1,947.93

Product Attribute Attribute Value Select Attribute
Altera
Product Category: CPLD - Complex Programmable Logic Devices
Delivery Restrictions:
 This item may require additional fees and documentation. Customs delays may also occur.
RoHS:  
EPM240
SMD/SMT
TQFP-100
1.8 V
192 Macrocell
80 I/O
- 40 C
+ 85 C
304 MHz
4.7 ns
Tray
Brand: Altera
Country of Assembly: Not Available
Country of Diffusion: Not Available
Country of Origin: US
Memory Type: Flash
Moisture Sensitive: Yes
Number of Logic Array Blocks - LABs: 24
Number of Logic Elements: 240
Operating Supply Current: 40 mA
Product Type: CPLD - Complex Programmable Logic Devices
Factory Pack Quantity: 90
Subcategory: Programmable Logic ICs
Supply Voltage - Max: 1.89 V
Supply Voltage - Min: 1.71 V
Total Memory: 8192 bit
Tradename: MAX II
Part # Aliases: 972850
Unit Weight: 9.419 g
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CNHTS:
8542399000
CAHTS:
8542390000
USHTS:
8542310055
JPHTS:
854239099
TARIC:
8542399000
MXHTS:
8542399901
ECCN:
EAR99

SoC FPGA Family

Altera SoC FPGAs integrate an Arm-based hard processor system (HPS) consisting of processors, peripherals, and memory interfaces with the FPGA fabric using a high-bandwidth interconnect backbone. The devices combine the performance and power savings of hard intellectual property (IP) with the flexibility of programmable logic. These user-customizable Arm-based SoC FPGAs are ideal for reducing system power, cost, and board size by integrating discrete processors and digital signal processing (DSP) functions into a single FPGA. They differentiate the end product with custom hardware and software and add support for virtually any interface standard or protocol in the FPGA.